1. Field of the Invention.
The present invention relates to the field of programmable logic devices, and more particularly, logic devices programmable to operate as state machines.
2. Prior Art.
Programmable logic devices (PLDs) of various designs and functions are now well-known in the prior art. Originally appearing as gate arrays to reduce the chip count in random logic circuits, various more sophisticated configurations are available to provide sequencing capabilities, branching capabilities, and the like. These devices however, in general have various limitations which effect their speed, ease of programming, or versatility in a number of applications. With respect to speed, popular processor clock rates are currently as high as 24 megahertz, with clock rates of the next generation processors undoubtedly being substantially higher. With the advent of the microprocessor based work stations and professional personal computers, there is a substantial need for state sequencer functions with greater than a 50 megahertz clock rate to provide the sub-system control and synchronizing for these systems, including the initiation of events which occur in mid system clock cycles to satisfy signal setup and hold conditions, as well the initiation of those which are synchronized with the system clock. Accordingly, there is a need for programmable state machine operative at clock rates well above 50 megahertz, though preferably expanded in sequencing capabilities over existing devices and easily programmable for a wide variety of applications.
Currently there is only one integrated circuit chip which operates at the frequency range of interest. That chip is the AMD PEG 2971. This device however, is not a state machine but a sequence generator (PEG standing for programmable event generator) and accordingly is not useful in all applications in which a state machine may be used. The AMD 29PL141, on the other hand, is a combined sequencer and ROM in a single package. This part permits assembler syntax programming and computed branching but is currently limited in speed to approximately 20 megahertz, and perhaps 30 megahertz in the future. In addition, in the 29PL141 the branch designations are constrained to the ROM section boundaries, whereas in the present invention there is no such limitation. In addition, the condition calculation permitted by the present invention covers more of the machine context than the 29PL141 calculation, as the present invention considers the entire input and state context compared to the 29PL141 calculation over one input. The 29PL141 has a 35 nanosecond setup and a 15 nanosecond clock to output.
The Signetics PLS parts are also relevant as prior art because they represent a customer accepted state machine architecture. The '105 and '167 parts have 48 product terms (PTs) leading into an array of OR terms which drive R-S flip-flops. The setup time of the Signetics parts is about 35 nanoseconds. In that regard, Texas Instruments has advertised a 50 megahertz part, though the setup and hold times place this part in the 33 megahertz range for state machine designs. Also Signetics recently introduced a 405 part which has a 15 nanosecond setup and a 10 nanosecond clock to output: conditional timings which can allow for operation at up to 40 megahertz. However, the PLUS405A has no Mealy outputs (i.e. no combinational outputs), no skew control or minimum timing and no sequencing via macrocells. Other problems faced by the device in 40 megahertz operation include the necessity to control two inputs to each register (the part uses twice the number of product terms of the present invention), the loading of product terms when registers are used as T-types which slows the device down and the nonutility of the compliment path above 30 megahertz which makes coding more difficult.
The Prose chip from MMI is a 30 megahertz sequencer with one or three way conditional branching. Its principle limitations are the setup time and the limited condition calculation circuitry. The SAM from Altera is a large sequencer consisting of a 256 location ROM and condition calculation/branch control circuitry. Its main feature is its large ROM though it is expected to run at less than 30 megahertz. Finally, D speed PALs are available which can be used as small state machines to run at speeds up to about 50 megahertz. Available devices are bipolar 8 output devices with high power requirements. The information capacity of an 8 register device is small, so usually several such devices need to be combined for a circuit
The purpose of the present invention is to provide an architecture which will result in a much faster programmable high speed state machine for a multitude of applications.